1. Field of the Invention
This invention relates to a boost circuit used in a semiconductor integrated circuit device such as a flash memory.
2. Description of Related Art
As electrically rewritable and non-volatile memories (i.e., EEPROMs), various kinds of types of flash memories are known such as NAND-type, NOR-type, DINOR-type and so on. Since it is required of these flash memories to generate various voltages higher than the power supply voltage in accordance with operation modes, boost circuits are usually integrally formed in the memory chip.
A boost circuit is usually formed of a charge pumping circuit, which is formed of transistors serving as charge transfer devices and capacitors serving as pumping devices. For example, as shown in FIG. 36, plural diode-connected NMOS transistors are connected in series between a power supply node and an output node, on which a boosted voltage is generated. Coupled to the respective connection nodes of the NMOS transistors are one ends of capacitors, which serving for controlling potentials of the connection nodes, respectively, by capacitive coupling. The other ends of the capacitors are applied with complementary clocks in such a way that even-numbered capacitors and odd-numbered ones are driven in the reverse phase. As a result, a boosted voltage higher than the power supply voltage is output on the output node (see, for example, FIG. 4 in Unexamined Japanese Patent Application Publication No. 2001-84783).
In the conventionally used, two-phase driving boost circuit, charge transfer between adjacent two capacitors is limited by threshold voltage Vth of the NMOS transistor. That is, with coupling gate to drain, the NMOS transistor serves as a diode for transferring charge in one direction. In this case, supposing that the drain and gate voltage is Vd, a voltage transferred to the source is limited to Vd-Vth.
Therefore, in case it is impossible to reduce the threshold voltage of the NMOS transistor in the boost circuit to a sufficiently low level due to restrictions on fabrication processes, ability thereof to transfer charge is limited so that it becomes difficult to generate a high voltage at a high rate. In addition, even if the threshold voltage is made low by a certain level, as the output voltage at the boost output node becomes higher, the threshold voltage of the NMOS transistor becomes higher due to a so-called substrate bias effect. Therefore, the charge transferring efficiency of each stage NMOS transistor is reduced, thereby reducing the boost rate.
To solve this problem, it is effective to make the capacitors large in capacitance. However, this leads to increase of the occupied area of the boost circuit.